Removing False Paths from Combinational Modules

The existence of false paths complicates the task of accurate timing analysis significantly. A technique to remove false paths from a combinational circuit without degrading its performance has a practical value since topological timing analysis is then good enough to estimate the performance of false-path-free circuits accurately. One can think of the KMS algorithm [1] as such a procedure. It takes a combinational circuit and arrival times at its primary inputs, and returns an equivalent irredundant circuit no slower than the original. One major problem is that it only guarantees the performance of the final circuit under the given arrival times; under different arrival time conditions the transformed circuit can be slower than the original. We propose a technique to remove false paths from a combinational module without slowing down the circuit under any arrival time condition. The procedure is particularly useful in the context of hierarchical synthesis. For example, if the same module is used more than once, the master module can be made false-path-free once and for all without affecting the performance of any instance. Even if a module is used only once, the procedure removes false paths safely without any knowledge on arrival times at the primary inputs. This makes it possible to synthesize the module before the surrounding design is fixed. We also show that the final redundancy removal of the KMS algorithm can slow down a circuit if the delay of the circuit is computed separately for each input pattern. Since replacing the original circuit with the irredundant one in a hierarchical circuit can worsen the delay of the entire circuit, redundancy removal is dropped to guarantee the delay-preserving property.